Advances in semiconductor processing and logic design have permitted an increase in the amount of logic that may be present on integrated circuit devices. As a result, computer system configurations have evolved from a single or multiple integrated circuits in a system to multiple hardware threads, multiple cores, multiple devices, and/or complete systems on individual integrated circuits. Additionally, as the density of integrated circuits has grown, the power requirements for computing systems (from embedded systems to servers) have also escalated. This ever increasing computing device energy consumption can strain power supply resources, particularly in systems having multiple compute nodes.
Multi-node compute systems (such as a rack of servers) often use a shared power supply (rather than a single power supply per node) to improve efficiency. Today such shared power supplies are required to be sized for the sum of the maximum peak power (Pmax) of all compute nodes connected to them. Although this maximum peak power occurrence is a rare event, it is required to be supported to prevent a system crash if all nodes do have a concurrent Pmax event. Designing a power supply to accommodate the sum of Pmax for each computing node increases system cost and power budget undesirably.